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TSMC Starts 3nm Production: A Long Node to Drive Industry-Leading Chips

TSMC’s 3nm production lags behind that of Samsung but leads that of Intel.

TSMC held a “Volume Production and Capacity Expansion Ceremony” at Fab 18 in the Southern Taiwan Science Park on Thursday (STSP). Fab 18 is where chips using the N3 (3nm-class) process technology are manufactured. The foundry asserts that the yields of the 3nm chips it mass-produces are satisfactory and that the N3 technology family will serve its clients for many years.

N3 in HVM

Early in September, TSMC reportedly initiated high-volume manufacturing (HVM) for its N3 fabrication process. Now that the first batch of chips has been manufactured and tested, the formal announcement about volume production is generally intended to demonstrate that the foundry’s 3nm-class process is suitable for mass production and yields ‘good’ chips. N3 is a crucial family of process technologies for TSMC, as it will be the foundry’s final general-purpose node based on FinFET transistors and a node that will serve its customers for at least ten years. TSMC claims that N3 and its successors will be used to manufacture $1.5 trillion worth of HVM products within five years.

Compared to TSMC’s N5 manufacturing technology, the company’s N3 production node promises a 10% to 15% improvement in performance (at the same power and transistor count), a 25% to 30% reduction in power consumption (at the same frequency and complexity), and a 1.6-fold increase in logic density. The SRAM bit-cell size of the N3 is 0.0199 m2, which is only 5% smaller than the SRAM bit-cell size of the N5 at 0.021 m2.

N3E vs N5 N3 vs N5
Speed Improvement @ Same Power +18% +10% ~ 15%
Power Reduction @ Same Speed -34% -25% ~ -30%
Logic Density 1.7x 1.6x
HVM Start Q2/Q3 2023 H2 2022

The first iteration of TSMC’s 3nm-class fabrication processes, N3, also known as N3B, is anticipated to be used exclusively by early adopters for a limited number of applications due to its narrow process window. This may result in lower yields for specific designs. According to media reports, the majority of TSMC’s clients are now lining up for N3E manufacturing technology, which improves process window, boosts performance, and reduces power consumption even further at the expense of SRAM scaling (i.e., lower transistor density). N3E appears to have a 0.021 m2 SRAM bit-cell, with minimal differences from N5. This will result in larger die sizes for SRAM-heavy designs (the vast majority of CPUs, GPUs, and SoCs).

N3 provides chip designers with FinFlex, a potent method for optimizing die sizes and performance/power consumption. FinFlex enables developers to mix and match various types of standard cells within a single block to precisely optimize performance, power consumption, and area, which will be especially appreciated by designers of complex system-on-chips that tend to maximize both transistor performance and transistor density.

TSMC intends to add more nodes to the N3 family in the future. The most recent versions of the process include N3P, which promises improved performance, N3S, which is designed to increase transistor density, and N3X, which features increased voltages and additional performance optimizations for applications such as CPUs.

Customers Are Queuing Up for N3 Despite Its Expensive Price

Almost all of TSMC’s most important customers, including AMD, Apple, Broadcom, Intel, MediaTek, Nvidia, and Qualcomm, are rumored to be interested in TSMC’s N3 nodes, though it is unclear when and with which products these chip designers will join the foundry’s 3nm bandwagon. Apple is anticipated to be one of the first clients to adopt TSMC’s N3 for one of its premium SoCs, although we do not know which SoC. In the meantime, AMD plans to adopt N3 for some of its Zen 5-based products scheduled for release in 2024, while Nvidia will likely adopt N3 for its next-generation Blackwell architecture-based GPUs scheduled for release around the same time.

However, the use of TSMC’s N3 will not be inexpensive. According to some reports, the contract chip manufacturer could charge up to $20,000 per wafer processed with its 3nm-class technology. TSMC’s pricing depends on a variety of variables, including quantities, designs, and specifications, so take this number with a grain of salt.

In the meantime, high quotes indicate that fabless chip designers may prefer to reserve TSMC’s leading-edge nodes for premium products while fabricating more mainstream devices with a tried-and-true fabrication technology. For instance, Apple only uses TSMC’s N4 (4nm-class) manufacturing process for the A16 Bionic processor that powers the iPhone 16 Pro. In contrast, the iPhone 14 non-Pro continues to utilize the A15 SoC manufactured using TSMC’s N5P technology.

Fab 18 Phase Eight

TSMC held a topping ceremony for the Fab 18 phase 8 building in addition to announcing that its N3 process technology had entered HVM. The company manufactures its most advanced chips on its N5 and N3 production nodes using it’s Fab 18. Once Fab 18 phase 8 is outfitted with production tools, it will substantially increase TSMC’s capacity for its cutting-edge fabrication processes.

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