According to industry sources, TSMC is considering lowering 3nm pricing to attract more chip designers.
Although TSMC’s N3 (3nm-class) family of fabrication processes offers several advantages in terms of performance and power consumption, the extremely high cost of the foundry’s initial N3 node prevents widespread adoption. According to a report by MyDrivers, the company is rumored to be preparing to reduce its prices for 3nm production to attract chip designers.
While any published TSMC N3 quotes and prices should be considered rumors at this time, TSMC’s N3E production costs will likely be lower than its initial N3 costs. How much the company will charge for production on other N3-class nodes, such as N3P, N3S, and N3X, remains to be seen. The lowering of 3nm production costs will attract more customers to these nodes, but this will not happen immediately.
Apple is rumored to be the sole user of TSMC’s initial N3 manufacturing technology (also known as N3B) because Apple is the foundry’s largest client willing to adopt cutting-edge nodes first. However, N3 is a costly technology to implement. According to China Renaissance, N3 uses extreme ultraviolet (EUV) lithography for up to 25 layers, and each EUV scanner now costs $150 million to $200 million, depending on the configuration. To depreciate fabrication facilities outfitted with such production equipment, TSMC must increase the price of its N3 process and successors.
Some claim that TSMC may be charging as much as $20,000 per N3 wafer, up from $16,000 per N5 wafer. While the accuracy of such estimates depends on several variables, it is clear that chip production costs continue to rise. Increased costs translate to decreased profits for companies such as AMD, Broadcom, MediaTek, Nvidia, and Qualcomm. As a result, chip developers are reevaluating how they create advanced designs and utilize leading-edge nodes.
“We believe the meaningful [N3] ramp-up will occur in the second half of 2023, when the optimized version, N3E, will be ready,” wrote China Renaissance analyst Szeho Ng. “We believe that its major HPC (AMD, Intel) and smartphone (QCOM, MTK) and ASIC (MRVL, AVGO, GUC) customers will remain in N4/5 and opt for N3E as their first foray into the N3 class. In the meantime, we believe the adoption of N3 (also known as N3B) will be primarily limited to Apple products.”
To encourage its partners to utilize its N3-class process technologies, TSMC is rumored to be contemplating a price reduction for these nodes. In particular, TSMC’s N3E process only uses EUV for up to 19 layers, has a lower manufacturing complexity, and is therefore less expensive to use. TSMC could reduce N3E production costs without impacting profitability. N3E offers no scaling advantages over N5 when it comes to SRAM cells, which results in larger die sizes compared to N3/N3B.
AMD announced publicly that it would use an N3 node for some Zen 5-based designs due in 2024, and Nvidia is expected to adopt N3 for its next-generation Blackwell architecture-based GPUs around the same time. Adoption of N3-class nodes is anticipated to be limited to a subset of products due to high costs; therefore, a reduction in prices will likely cause chip designers to reconsider their adoption strategy.
Low yields are another issue with TSMC’s N3 chip. Some estimates place yields between 60% and 80%, while DigiTimes sources (via Dan Nystedt) indicate they’re below 50%. However, given that only Apple is rumored to use this manufacturing technology and the company’s reputation for secrecy, any information regarding the yields of initial N3 chips should be taken with a large grain of salt.