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Intel Says Moore’s Law Is Alive And Well With Trillion Transistor Chips Coming By 2030

Much has been written about Moore’s Law’s demise. The “law”—more properly titled an “observation”—was created by one of Intel’s founders, Gordon Moore. He observed that the number of components in an integrated circuit roughly doubled every year, but in 1975 he revised his observation to every two years. While progress on that front has undeniably slowed, Intel has no intention of abandoning Moore’s Law, and it plans to demonstrate how it will keep things shrinking at IEDM.

IEDM is an abbreviation for the IEEE International Electron Devices Meeting. It’s an annual conference where companies like Intel and TSMC present their latest findings in “semiconductor and electronic device technology, design, manufacturing, physics, and modeling.” In other words, it’s a venue for companies to showcase their latest and upcoming processor and device fabrication technologies. IEDM 2022 is currently underway, and Intel is making some big promises.

The most significant is, of course, one trillion transistors on a package by the next decade. In comparison, the densest chip available is NVIDIA’s AD102, which is used in the GeForce RTX 4090, and it only has 76.3 billion transistors. To reach one trillion, enormous advances in microprocessor fabrication will be required. Regular readers may recall that Intel CEO Pat Gelsinger pledged to advance five nodes by 2025 and that the company’s foundry division was given “unlimited” resources to do so.

According to what Intel brought to the IEDM show and tell, those efforts appear to be bearing fruit. The company’s main focus is on three key areas: 3D packaging technology, ultra-thin materials science advancements, and entirely new types of processors.

Chiplet-based (or “disaggregated”) processors currently have two distinct stages: the chiplets are manufactured like any other microprocessor, and then those chiplets are meticulously assembled into a complete package. According to Intel, the goal is to “blur the line” between these two stages, allowing for greater connectivity between chiplets. When discussing the fanout interface between chips on its Navi 31 GPUs, AMD made similar remarks.

Chips made with Intel’s next-generation technology are referred to as “quasi-monolithic” because the hybrid bonding used, when scaled to a 3m interconnect pitch, appears to provide similar bandwidth to the same features found on monolithic SoCs. Despite this, the interconnects appear to be flexible in the sense that they can be used to connect to different chiplets, allowing for product design flexibility.

The primary reason that Moore’s Law’s progress has slowed in the last decade is that we are approaching the physical limits of traditional silicon fabrication. Intel intends to push past those boundaries by employing novel materials such as hafnia and molybdenum disulfide. These materials are referred to as “2D materials” because they are relatively simple to shape into the complex structures required for microprocessors while remaining flat.

Many articles have been written about the use of graphene in transistors, but despite its many appealing properties, graphene lacks one critical feature: a natural bandgap. That means that to make graphene transistors, you must create your bandgap, which is problematic for a variety of reasons. Instead, Intel is considering stacking 2D nanosheets with less exotic materials that have an inherent bandgap, allowing them to make nanosheets only 3 atoms thick.

When faced with a problem, you can either try to improve the performance of your current solution or try a new one. Intel is currently pursuing both approaches, and one example of the latter is stacked FeRAM. Ferroelectric RAM isn’t new in and of itself, but it hasn’t seen much use because of its extremely low density when compared to flash memory and DRAM.

Intel first proposed 3D-stacked FeRAM in 2020, but it has since made a breakthrough in FeRAM scaling by stacking ferroelectric capacitors. This is the first demonstration of stacked array capacitors that can match the performance of conventional trench capacitors, according to Intel. Because FeRAM is fast, efficient, and non-volatile, the company believes it holds great promise for the future of embedded memory.

As the number of transistors increases, so does the power consumption of ever-denser chips. Intel is also working to combat this through advances in materials science. Gallium Nitride (GaN) semiconductors are popular in RF applications because they can handle significantly more power and frequencies than traditional silicon chips.

In terms of power efficiency, Intel claims that its new GaN-on-Si technology outperforms the competition by a factor of 20. Furthermore, the company claims to have achieved a cut-off frequency of 680 GHz, which will enable the development of ever-faster wireless technology beyond today’s 5G. While GaN-on-Si is relatively expensive, Intel claims to have a “viable path” to producing it on 300mm wafers. This should significantly reduce costs.

According to the slide above, Intel is commemorating the 75th anniversary of the transistor. Intel has undeniably been a driving force in the development of our modern world, and the company’s research arm has been at the cutting edge of semiconductor technology for the majority of its history. In practice, Chipzilla may have lagged behind TSMC, but it’s clear that the people in charge understand the importance of cutting-edge fabrication technologies.

The company’s current products are manufactured on “Intel 7,” but its 14th-generation Meteor Lake chips are expected to hit tape out on Intel 4 any day now, putting their release early next year. Following Intel 4, there is a refinement called “Intel 3,” and then a new process called “20A” follows. Intel claims that the 20A refinement, known as 18A, will be ready by 2025. That will be an impressive feat, but we, like everyone else, are eager to see renewed competition in the foundry space.

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