Intel announced last year that it would take process leadership from TSMC and Samsung Foundry by 2025. TSMC and Samsung are currently the world’s top two chip foundries, both shipping the most cutting-edge chips. Both will deliver chips manufactured on the 3nm process node next year. Let’s keep things as straightforward as possible. The smaller the process node, the smaller the transistors used to power a chip, allowing for more to be crammed inside.
Generally, the more transistors a chip has, the more powerful and energy-efficient it is
The more transistors there are inside a chip, the more powerful and energy-efficient it is. As an example, consider the iPhone. The A13 Bionic SoC, which was released in 2013, was used in the iPhone 11 series and was manufactured using TSMC’s 7nm process node. There were 8.5 billion transistors on the chip. The A16 Bionic chip, which powers the iPhone 14 Pro and iPhone 14 Pro Max, is built on TSMC’s 4nm process node (technically an improved 5nm process) and contains nearly 16 billion transistors.
Three Research Focus Areas: Paving clear paths and exploring options for more powerful computing
- New 3D packaging technology enables seamless integration of “chiplets”
- Intel looks to super thin, 2D materials to fit more transistors onto a single chip
- New possibilities in energy efficiency and memory for higher performing computing
TSMC and Samsung could be producing 2nm chips by 2025, with the latter already talking about producing 1.4nm chips by 2027. TSMC has mentioned 1nm chips but has not specified when they will be available. But Intel is not to be dismissed, and at IEDM 2022 (International Electron Devices Meeting), the company announced plans to put one trillion transistors on a package by 2030 to commemorate the 75th anniversary of the invention of the transistor.
A package is a container in which chips are placed. They are either soldered to or plugged into a printed circuit board (PCB). Unless it is a Multi-Chip Module, a package contains only one chip die. An eMMC flash card, which contains flash memory and a flash memory controller, is an example of this.
Intel claims it will be able to maintain Moore’s Law; this is the observation made by Intel co-founder Gordon Moore, who originally predicted that the transistor count in chips would double every year. Moore revised this ten years later, anticipating that transistor counts would double every other year by 1975. Intel will benefit from having the first crack at the High Numerical Aperture Extreme Ultraviolet Lithography machine, which is designed to etch thin circuitry patterns on wafers that become chips.
How Intel intends to reclaim process leadership
The new machines will enable foundries to etch circuitry designs at higher resolutions, allowing for 1.7x smaller chip features and 2.9x higher chip density. Each machine costs somewhere in the neighborhood of $300 million. “Seventy-five years after the invention of the transistor, innovation driving Moore’s Law continues to address the world’s exponentially increasing demand for computing,” said Gary Patton, Intel vice president, and general manager of Components Research and Design Enablement.
“At IEDM 2022, Intel is showcasing both the forward-thinking and concrete research advancements required to break through current and future barriers, deliver to this insatiable demand, and keep Moore’s Law alive and well for years to come,” Patton continued.
The replacement of FinFET transistors with Gate-All-Around transistors is one of the industry’s most significant discoveries (GAA). In contrast to FinFET (which TSMC is still using for its 3nm process node), current flows can be manipulated on all four sides of the channel and will be implemented using vertically stacked nanoribbons. Samsung uses GAA for its 3nm chips, while TSMC will not use it until it begins producing 2nm chips in a few years. Intel, which calls its GAA technology RibbonFET, plans to ship such chips in 2024.
Innovations in chip packaging with a 10x improvement in density are also assisting Intel in its goal of producing packages with one trillion transistors. This will result in a significant increase in the number of transistors that can be packed into a small space. And new materials to aid in the production of smaller transistors include the use of a super-thin material made up of only three atoms!
